This invention relates to a unique single board computer system operable as a system master and a bus target and methods of operating the same.
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A typical computer system includes a central processing unit (CPU) (or host processor), memory and an input/output (I/O) controller. These modules are mounted on a printed circuit board and are connected together by buses. Buses are shared communication channels that carry information between the components of the computer system. The signals that are carried by a bus may include address signals, data signals, clock signals and other control signals. Standard system buses, such as the AT bus, the Peripheral Component Interconnect (PCI) bus, the Small Computer System Interface (SCSI) bus, the Industry Standard Architecture (ISA) and the Extended ISA (EISA) bus, are used to transmit data between the different boards of a computer system, including a motherboard and one or more expansion boards. The motherboard is the main circuit board of a computer system. A motherboard typically contains connectors for attaching additional boards (e.g., expansion boards or daughter boards) to the system, and typically includes a system master. The system master manages and controls the system configuration. The system master controls the configuration of all of the system resources and is the only component in the system that has knowledge of the bus topology and the address transmission mechanisms. The system master and one or more bus controllers (or bus masters) emit address and control signals to the system buses. A separate bus arbiter arbitrates for control of the system bus. A bus master is a device (e.g., a processor) that takes control of a system bus to initiate a transaction after being granted access to the bus by the arbiter; a device at the other end of the transaction is referred to as a bus target. The information transferred in bus transactions between bus masters and bus targets include data, address information, commands, byte enables and device identification information.
The invention features a single board computer system operable indifferently as a system master, and a bus target and methods of operating the same.
In one aspect, the invention features a system comprising a processor mounted on a printed circuit board and having a system master mode of operation and a bus target mode of operation. An expansion board connector is coupled to the processor and is configured to couple to an expansion board. A system master connector also is coupled to the processor and is configured to couple to an expansion board connector of a system master board.
Embodiments may include one or more of the following features.
A mode detector preferably is coupled to the processor and is configured to generate a mode control signal for controlling the operating mode of the processor. The mode detector preferably is configured to determine whether the system is coupled to an expansion board or a system master board. In one embodiment, the mode detector is coupled to the system master connector and is configured to produce a mode control signal based upon a signal at a terminal of the system master connector. In this embodiment, the mode detector is configured to produce a bus target mode control signal if a power terminal of the system master connector is active, and is configured to produce a system master mode control signal if a power terminal of the system master connector is inactive.
The system may include a bus controller configured to enable a master bus in a system master mode of operation and to enable a target bus in a bus target mode of operation. The bus controller preferably is configured to generate a master clock signal in the system master mode of operation and to disable a master clock signal in the bus target mode of operation. The bus controller may be configured to reset a bus target in the system master mode of operation.
An input/output (I/O) controller may be mounted on the printed circuit board. The I/O controller preferably is operable to interface the processor to a system master bus in a system master mode of operation and to interface the processor to a target bus in a bus target mode of operation.
In one embodiment, a second expansion board connector is coupled to the processor and is configured to couple to a second expansion board. The system may include a bus arbiter configured to grant bus access to a bus master by arbitrating between bus requests received from the first and second expansion boards.
The expansion board connector and the system master connector preferably are compliant with a bus protocol that supports bus masters and bus targets. In one embodiment, the expansion board connector and the system master connector are compliant with a Peripheral Component Interconnect (PCI) bus protocol.
In another aspect, the invention features a method of operating the above-described system. In accordance with this inventive method a processor is configured as a system master or a bus target in response to a received mode control signal, and a target bus or a system master bus is selectively enabled in response to the received mode control signal.
A mode control signal may be generated based upon a connector terminal signal at a terminal of a connector. The connector terminal signal may be detected at a power terminal of a system master connector. A master bus may be enabled by enabling a master clock signal and a bus target reset signal.
Among the advantages of the invention are the following.
The invention provides a single board computer system with a universal board architecture that enables the system to be used flexibly as either a bus target or a system master. The invention is particularly advantageous when implemented as an evaluation board. For example, the bus target mode of operation enables designers to write software code on a conventional computer system and readily test and debug the operation of the software code on a target processor incorporated into the inventive single board computer system. The system master mode of operation enables designers to incorporate the target processor into a prototype computer system that includes the added functionality of one or more expansion boards. In sum, the invention enables designers to quickly and easily test and debug prototype computer systems with a single board, avoiding the additional time and expense that otherwise would be entailed if two separate boards were used. Furthermore, the invention reduces the costs and efforts needed to develop, maintain and support the two modes of operation provided by the invention.
Other features and advantages of the invention will become apparent from the following description, including the drawings and the claims.